| 摘要 |
PURPOSE: To attain stable arithmetic bit accuracy independently of a reception level of plural carriers by using a level detection circuit in time division so as to control reception in a way of allowing a level difference between carriers in the case of receiving plural carriers. CONSTITUTION: The receiver is made up of a receiver 101, an A/D converter 102, frequency converters 103 to 106, FIR filters 107 to 110, a coefficient storage element 111, a scaling circuit 112, a control circuit 113, a timing clock generator 114, shift circuits 115 to 118, a level detection circuit 119 and a demodulation means 120. In the case of receiving four wave signals by the level detection circuit 119, a multiplexer in the circuit selects one by one each output from the four shift circuits 115 to 118 sequentially and repeats it for a prescribed time interval to receive the output of each shift circuit as a time-division multiplex signal. In the case of receiving one wave, the multiplexer continues selecting an output of the shift circuit 115 in operation. Number of bits for wiring is not increased. |
