| 摘要 |
A serial/parallel converter 2-converts a B channel data in an ISDN into an 8-bit parallel data and outputs it to a latch circuit 3. A comparator 4-compares an octet data latched by the latch circuit 3 with a preset idle pattern and, when the octet is different from the preset idle pattern, outputs a disaccord signal to a pulse generator 5. When an idle pattern appears continuously on the B channel, a timer circuit 6 outputs a significant signal. With using the significant signal from the timer circuit 6, it is possible to judge that the B channel is in non-use state, so that it can be determined by the simple circuit construction whether or not the B channel is in the use state. |
