发明名称 |
Efficient fill-buffer data forwarding supporting high frequencies |
摘要 |
A Fill Buffer (FB) based data forwarding scheme that stores a combination of Virtual Address (VA), TLB (Translation Look-aside Buffer) entry# or an indication of a location of a Page Table Entry (PTE) in the TLB, and a TLB page size information in the FB and uses these values to expedite FB forwarding. Load (Ld) operations send their non-translated VA for an early comparison against the VA entries in the FB, and are then further qualified with the TLB entry# to determine a “hit.” This hit determination is fast and enables FB forwarding at higher frequencies without waiting for a comparison of Physical Addresses (PA) to conclude in the FB. A safety mechanism may detect a false hit in the FB and generate a late load cancel indication to cancel the earlier-started FB forwarding by ignoring the data obtained as a result of the Ld execution. The Ld is then re-executed later and tries to complete successfully with the correct data. |
申请公布号 |
US9418018(B2) |
申请公布日期 |
2016.08.16 |
申请号 |
US201414337211 |
申请日期 |
2014.07.21 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
Sundaram Karthik;Gopal Rama;Chinnakonda Murali |
分类号 |
G06F12/10;G06F12/08;G06F9/38 |
主分类号 |
G06F12/10 |
代理机构 |
Renaissance IP Law Group LLP |
代理人 |
Renaissance IP Law Group LLP |
主权项 |
1. A method comprising:
determining whether there is a hit in a first level of cache memory for a processor when a Load (Ld) instruction is processed for a first execution; and in the absence of the hit in the first level of cache memory, storing the following in a Fill Buffer (FB) of the processor:
a first Virtual Address (VA) provided by the Ld instruction, anda first indication of a location of a first Page Table Entry (PTE) in a Translation Look-aside Buffer (TLB) of the processor, wherein the first PTE is associated with the first VA provided by the Ld instruction. |
地址 |
KR |