Data processing system having a control device for controlling an intermediate memory during a bulk data transport between a source device and a destination device.

摘要

In a data processing system a control device is described for an intermediate memory (14) during a bulk data transport between two data devices (10, 28). The first data device addresses a number of descriptor signals (D). Each descriptor signal indicates another descriptor signal, so that a sequence is formed which is cyclically coupled end-around. The descriptor signals indicate either a memory section (16-24) or a branch to a remote address in the memory. The memory sections used may thus be distributed throughout the memory. Additional descriptor signals indicate, in a direct or indirect manner, a descriptor signal of the sequence for each of the two data devices. A handshake by way of signal bits is present at the level of the memory sections.