发明名称 |
METHOD AND SYSTEM FOR DECREASING POWER CONSUMPTION INSIDE ELECTRONIC CIRCUIT |
摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the power consumption inside an electronic circuit by respectively fetching a prescribed number of instructions from a memory for every cycle of a fetch circuit during the operation of the fetch circuit in 1st and 2nd power modes. SOLUTION: While the fetch circuit is operated in the 1st power mode, N (N is the integer of N>1) pieces of instructions are fetched at a maximum from the memory for every cycle of the fetch circuit. While the fetch circuit is operated in the 2nd power mode, M (M is the integer of N>M>0) pieces of instructions are fetched at a maximum from the memory for every cycle of the fetch circuit. When a special power mode is started, for example, a processor 10 decreases the maximum number of instructions to be fetched within a single cycle, changes the operation of an LSU 28 and decreases the number of 'ways' of an instruction cache 14 and a data cache 16 inside these caches so that the power consumption is reduced.</p> |
申请公布号 |
JPH10143297(A) |
申请公布日期 |
1998.05.29 |
申请号 |
JP19970265942 |
申请日期 |
1997.09.30 |
申请人 |
INTERNATL BUSINESS MACH CORP <IBM> |
发明人 |
LOPER ALBERT J;SUUMUYA MALIK |
分类号 |
G06F1/26;G06F1/04;G06F1/32;G06F9/30;G06F9/38;G06F15/78;(IPC1-7):G06F1/32 |
主分类号 |
G06F1/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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