发明名称 METHOD FOR DESIGNING MICROPROCESSOR SOFTWARE CORE WITH VARIABLE HARDWARE SCALE
摘要 PROBLEM TO BE SOLVED: To eliminate H/W blocks which are unnecessary for software(S/W) processing for a microprocessor (μP) by determining a hardware(H/W) subelement obtained and determining a scale when the total time needed to execute decomposed microcodes is equal to or shorter than a software(S/W) process upper-limit time. SOLUTION: The clock period of aμP software core is given as information (step S3) and the execution processing time obtained from the number of S/W program processing steps is compared with a system request performance (step S5). When the processing tine has margin for system request performance, a microcode which performs other equivalent processes using no exclusive H/W block is substituted for (step S6). A system processing time, on the other hand, is calculated (step S14) and compared with a system processing restriction time (step S15). When the system processing restriction time is not exceeded and the processing can be performed, a multiplier is unnecessary finally and the area reduction of theμP software core is determined (step S17).
申请公布号 JPH10326291(A) 申请公布日期 1998.12.08
申请号 JP19970133133 申请日期 1997.05.23
申请人 MITSUBISHI ELECTRIC CORP 发明人 OTSUJI AKIO
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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