| 摘要 |
FIELD: automation and computer engineering. SUBSTANCE: device has first converter of binary code to compressed code, group of AND gates, group for halving in compressed code, which has group of AND gates, group of PROHIBITION gates, and OR gate. Diagonal matrix of delay gates and converter of unitary code to binary code are introduced to accomplish the goal of invention. Outputs of converter of unitary code to binary code are connected to outputs of group of AND gates from halving unit. Outputs of converter are connected to inputs of first delay gates from corresponding lines of diagonal matrix of delay gates. Outputs of delay gates are connected to inputs of subsequent delay gates in this line. Outputs of last delay gates in lines are connected to second group of inputs of converter of unitary code to binary code. EFFECT: simplified design. |
