Host interleaved erase operations for flash memory controller

摘要

This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage. The disclosed techniques are especially useful for direct-attached and/or network-attached storage.

主权项

1. A flash memory controller integrated circuit to receive memory access requests from a host, and to control a flash memory die, the flash memory die comprising independently erasable units of memory cells and for each one of the independently erasable units, independently programmable units of memory cells, the flash memory controller integrated circuit comprising:
at least one host interface to receive the memory access requests from the host and to exchange data with the host in association with the memory access requests; at least one memory interface to program the data into the flash memory die, and to read the data therefrom, in fulfillment of the memory access requests; circuitry to control performance of the memory access requests via the at least one memory interface; circuitry to track page release state of each of the independently programmable units in the flash memory die, and to track erase state for each of the independently erasable units in the flash memory die; circuitry to unsolicitedly transmit to the host via the at least one host interface information identifying the need for a maintenance operation to erase one of the independently erasable units, where the corresponding erase state indicates an unerased condition of the one of the independently erasable units, and where the corresponding page release states indicate that there are no unreleased pages of data still stored in the one of the independently erasable units; circuitry to receive from the host via the at least one host interface an erase command responsive to the information transmitted to the host identifying the need for the maintenance operation, the erase command being interleaved with the memory access requests from the host, the erase command to be performed to recycle the one of the independently erasable units where the corresponding erase state indicates the unerased condition and where the corresponding page release states indicate that there are no unreleased pages of data still stored in the one of the independently erasable units; and circuitry to control via the memory interface erasure of the one of the independently erasable units responsive to the erase command; wherein the flash memory controller integrated circuit is dependent on receipt of the erase command from the host for purposes of scheduling erase of the one of the independently erasable units.