Managing wait states for memory access

摘要

A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request.

主权项

1. A method comprising:
receiving a first edge of a latch signal from a non-volatile memory device that indicates a start of a memory access performed by the non-volatile memory device; receiving a first edge of a system bus clock signal that corresponds to a start of a first cycle of the system bus clock; based on the first edge of the latch signal and the first edge of the system bus clock signal, setting a latch delay signal to a first state; conditioned on the latch delay signal being in the first state, setting a system bus data ready signal to the first state to indicate an initiation of a wait state for a central processing unit (CPU), wherein the wait state is associated with reading data from the non-volatile memory device, and wherein the latch delay signal is distinct from the system bus data ready signal; receiving a second edge of the latch signal from the non-volatile memory device that indicates that data is available; and based on the second edge of the latch signal and the system bus clock signal, setting the system bus data ready signal to a second state to indicate completion of the wait state for the CPU.