Instruction and logic for adaptive dataset priorities in processor caches

摘要

A processor includes a front end, a cache, and a cache controller. The front end includes logic to receive an instruction defining a priority dataset. The priority dataset includes ranges of memory addresses each corresponding to a respective priority level. The cache controller includes logic to detect a miss in the cache for a requested cache value, determine a candidate cache victim from the cache, determine a priority of the requested cache value and the candidate cache victim according to the priority dataset, and evict the candidate cache victim based on a determination that the priority of the candidate cache victim is less or equal to the priority of the requested cache value.

主权项

1. A processor, comprising:
a front end including circuitry to receive an instruction defining a priority dataset, the priority dataset including a plurality of ranges of memory addresses, each range corresponding to a respective priority level; a cache; and a cache controller, including circuitry to:
detect a miss in the cache for a requested cache value;determine a candidate cache victim from the cache;determine a priority of the requested cache value according to the priority dataset;determine a priority of the candidate cache victim according to the priority dataset;evict the candidate cache victim based on whether the priority of the candidate cache victim is less than or equal to the priority of the requested cache value;maintain a first count of previous evicted cache victims with higher priority than respective previous requested cache values;maintain a second count of previous evicted cache victims with lower or equal priority than respective previous requested cache values; andadjust eviction policies based upon the first count and the second count.