发明名称 ARITHMETIC UNIT
摘要 PURPOSE:To shorten the processing time and to increase the processing speed by obtaining the subtraction result of characteristic parts as a negative or positive number and using a control signal to justify mantissa parts of data by barrel shifters and using a signal indicating magnitude relations between characteristic parts to select the mantissa parts of data and outputs of barrel shifters. CONSTITUTION:A binary subtraction result H and a signal I indicating magnitude relations between index parts are outputted by a subtracting circuit 11 to which the index part M1 of a first floating-point data and the index part M2 of a second floating- point data are inputted as the minuend and the subtrahend respectively. A control signal J to control the extent of shift is generated by a decoder 17 to which the result H is inputted, and the control signal J is used to justify the mantissa part N1 of the first floating-point data assuming that the result H is a negative number, and the mantissa part N2 of the second floating-point data is justified assuming that the result H is a positive number. The signal I is used to select the mantissa part N1 and the output F of a barrel shifter 12 by a selecting circuit 14, and the fixed-point part N2 and the output G of a barrel shifter 13 are selected by a selecting circuit 15. Thus, the processing time required for justification of floating-point data is shorted and the processing speed is increased.
申请公布号 JPS63170733(A) 申请公布日期 1988.07.14
申请号 JP19870002269 申请日期 1987.01.08
申请人 MITSUBISHI ELECTRIC CORP 发明人 SAKASHITA NORIYOSHI;SHIMAZU YUKIHIKO
分类号 G06F7/00;G06F7/76 主分类号 G06F7/00
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