| 摘要 |
A semiconductor memory device comprises a plurality of word lines (WL1, WL2), a plurality of bit lines (BL1, BL''), a plurality of memory cells (MC11, MC12) each includes a transistor (9) formed on a first semiconductor region (3) and having a floating gate (6), a control gate (8) connected to one of said word lines, a source region (5s) and a drain region (5d) connected to a first end of one of said bit lines, and further comprises a source line (SL) having a first capacitance thereof different from a second capacitance which is associated with said bit lines (BL1, BL2) and having a first end thereof connected to said source region, a first bias means (14) for charging said bit lins and said source line via said first semicondictor region to a high voltage level (Vcc) during a first time period and supplying a low voltage level (Vss) to said first semiconductor region during a second time period thereafter, wherein said low voltage level causes a voltage difference and a current between said source and drain region according to a difference between said first and second capacitance, by which current electrons are injected to said floating gate.
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