| 摘要 |
a first delaying circuit(210) delaying a digital image signal; a filter means(220/1-220/n) having plural filter parts which generate filter coefficients by controlling tab gain coefficients variably and delay data delayed variably again; a register(230) storing the re-delayed data; an adding means(240/1-240/n) adding each filter coefficient and each stored data corresponding to each filter coefficient in sequence; a second delaying circuit(241) delaying the final output of the adding means; a third delaying circuit(242) delaying cascade data; and a forth delaying circuit(245) supplying an digital/analog converter with the output data from which ghost is removed after delaying the output data.
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