发明名称 Semiconductor processing methods of forming integrated circuitry, forming conductive lines, forming a conductive grid, forming a conductive network, forming an electrical interconnection to a node location, Forming an electrical interconnection with a transistor source/drain region, and integrated circuitry
摘要 In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally spaced from the diffusion region. The conductive line is preferably formed relative to and within isolation oxide which separates substrate active areas. The conductive line is subsequently interconnected with the diffusion region. According to another preferred implementation, an oxide isolation grid is formed within semiconductive material. Conductive material is formed within the oxide isolation grid to form a conductive grid therein. Selected portions of the conductive grid are then removed to define interconnect lines within the oxide isolation grid. According to another preferred implementation, a plurality of oxide isolation regions are formed over a semiconductive substrate. Conductive material is formed which is received within at least one of the isolation regions. In one preferred implementation, a silicon-on-insulator (SOI) substrate is utilized to support integrated circuitry which is formed utilizing the methodical aspects of the invention. In another preferred implementation, other substrates, such as conventional bulk substrates are utilized.
申请公布号 US2002001885(A1) 申请公布日期 2002.01.03
申请号 US20010848825 申请日期 2001.05.03
申请人 NOBLE WENDELL P. 发明人 NOBLE WENDELL P.
分类号 H01L21/768;H01L21/8242;H01L21/84;H01L23/52;H01L27/12;(IPC1-7):H01L21/00 主分类号 H01L21/768
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