发明名称 |
ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME |
摘要 |
An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern. |
申请公布号 |
US2016181318(A1) |
申请公布日期 |
2016.06.23 |
申请号 |
US201514789428 |
申请日期 |
2015.07.01 |
申请人 |
SK hynix Inc. |
发明人 |
Dong Cha-Deok;Park Ki-Seon;Lee Bo-Mi;Choi Won-Joon;Kim Guk-Cheon;Kim Yang-Kon |
分类号 |
H01L27/22;G06F12/08;H01L43/02 |
主分类号 |
H01L27/22 |
代理机构 |
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代理人 |
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主权项 |
1. An electronic device comprising a semiconductor memory, wherein the semiconductor memory includes:
a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern and having a sidewall aligned with the variable resistance pattern while including a non-metallic material which prevents a penetration of a wet chemical. |
地址 |
Icheon-Si KR |