Operand fetching control as a function of branch confidence

摘要

Data operand fetching control includes a computer processor that includes a control unit for determining memory access operations. The control unit is configured to perform a method. The method includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction resides in the pipeline relative to other instructions in the pipeline. The method also includes mapping the summation weight value of a selected instruction that is attempting to access system memory to a memory access control, each memory access control specifying a manner of handling data fetching operations. The method further includes performing a memory access operation for the selected instruction based upon the mapping.

主权项

1. A computer program product for operand fetching control in a computer processor pipeline of a processor having a data cache to store operands fetched by load/store instructions, the computer program product comprising:
a tangible, non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: calculating a summation weight value for each instruction or group of instructions in the computer processor pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction or group of instructions reside in the computer processor pipeline relative to other instructions in the computer processor pipeline; mapping, by a control unit logic of the computer processor pipeline, the summation weight value of a selected load/store instruction in the computer processor pipeline that is attempting to access system memory to one of a number of distinct pre-defined ranges of summation weight values, each of the pre-defined ranges of summation weight values corresponding to a respective memory access control, each of the memory access controls specifying a different manner of handling an operand fetching operation from the data cache, wherein each manner of handling defines a respective depth in a cache hierarchy of the data cache that an operand fetch is permitted to access; receiving the mapped memory access control for the selected load/store instruction from the control unit logic by a load-store unit of the computer processor pipeline via an interface between the control unit logic and the load-store unit; and performing a memory access operation for the selected load/store instruction based on the manner of handling the operand fetching operation that is specified by the received mapped memory access control by the load-store unit.