发明名称 SYSTEMS, APPARATUSES, AND METHODS FOR SYNCHRONIZING PORT ENTRY INTO A LOW POWER STATUS
摘要 Systems, apparatuses, and method for synchronizing port entry into a lowest power state are described. All logic of a port placed into an intermediate state prior to entry into the lowest power state.
申请公布号 US2016259400(A1) 申请公布日期 2016.09.08
申请号 US201615158271 申请日期 2016.05.18
申请人 Intel Corporation 发明人 Wagh Mahesh;Lim Su Wei
分类号 G06F1/32;G06F13/42;G06F9/44 主分类号 G06F1/32
代理机构 代理人
主权项 1. An apparatus comprising: a transmitter; a receiver; a power controller to transition the transmitter and the receiver to a low power state, wherein the power controller to transition the transmitter and the receiver to a low power state, the power controller operable to halt a data transfer rate state of a device;transition the receiver and the transmitter to a first power saving state in response to the data transfer rate state being halted;in response to the receiver and the transmitter being in the first power saving state, transition the receiver to a second power saving state in which configuration state for the first receiver and the first transmitter is maintained, the second power saving state being a lower power consumption state than the first power saving state;in response to the receiver transitioning to the second power saving state that is to maintain configuration state for the receiver and the transmitter, transition the transmitter to the second power saving state.
地址 Santa Clara CA US