Feldeffekttransistor-Bauelement

摘要

1276463 Photoresponsive semi-conductors INTERNATIONAL BUSINESS MACHINES CORP 6 Jan 1970 [15 Jan 1969] 571/70 Heading H1K A photoresponsive insulated gate FET comprises a P-type substrate 10 containing diffused N-type regions 12, 14 defining PN junctions 16, 18; the substrate being covered by SiO 2 layer 20. Ohmic contacts 22, 24 are made to the PN junctions which are bridged by a gate 26 overlying the SiO 2 layer. A source-drain potential source Vd is connected positively to source contact 24 and negatively to drain contact 22, while gate 26 is connected to region 12 over ohmic contact 28. Light incident on the source penetrates through regions 12 and 14 to the junctioning 16 and 18, while an external voltage source is connected positively to 22 over resistance 32 and negatively to 10 over resistance R S ; the voltage across the substrate biasing the FET "off" by substrate potential V SUB . On incidence of light from 30, the reverse bias current increases to develop a further voltage drop across R SUB formed by the geometry of the source junction, and it is shown by mathematics that current gain bandwidth is given by where gsm = substrate transconductance C = C(O)A W = channel width A = source junction area L = source-drain distance Á = surface mobility V SUB = substrate potential Vd = source/drain potential and is inversely proportional to transistor size i.e.(W/A #1/W). The source junction area may be square of side W and channel length L; the source drain and series resistance R S being formed by a shallow square diffusion permitting incident light to penetrate the surface through an anti-reflection coating (Fig. 2, not shown). In an application (Fig. 3) the phototransistor comprises gate 36 receiving signals to control current between source 38 and drain 40, and is biased "off" by V 0 over series resistor R S . A load FET 42 is connected between transistor 36 and B+ source, while FET's 44, 46 constitute an inverter driven by the combination of 36 and 42. The net current gain is given by g8m ggm R s 2, where gm is transconductance of driven circuit, R SUB is determined by source junction design, and adjustment of R S varies speed of response and resistivity, so that the change in current between source and drain exceeds the change in reverse bias current. The circuit and an array of circuits may be integrated and the gate electrode may be utilized to initiate logical functions.