| 摘要 |
PURPOSE: To considerably reduce the operation volume while securing the sufficient performance in the aspects of leading-in time and jitter and to prevent the sampling speed from being restricted by the data rate in the clock reproducing processing of a digital demodulator used for π/4 shift QPSK modulation. CONSTITUTION: A timing discrimination circuit 31 discriminates the timing when reproduced data before π/4 reverse shift takes ±1 OR 0} for each of actual and virtual eye patterns after detection of a π/4 shift QPSK modulation wave. A sign discrimination circuit 32 discriminates whether values preceding and following the reproduced value on the data side where the reproduced value (estimated value) is estimated to be '0' have different signs at this discriminated timing or not. A phase error direction discrimination circuit 33 determines the phase error direction based on this discrimination result. A phase error correction circuit 34 generates an interpolation filter control value in accordance with this phase error direction. |
