发明名称 Low output impedance stage for capacitive or direct coupling.
摘要 This output stage consists of an emitter-follower transistor (T) biased by a current source (T3). This current source is traversed by a current I substantially equal to n times the current Io of a reference current source in the case of capacitive coupling with a load (R). If the coupling with the load (R) is resistive, a set of transistors (T4, T5, T6) causes the base current to the transistor (T3) to be cancelled and the biasing of the transistor (T) occurs directly through the resistive load. Application to the output stages of power amplifying circuits for video stages. <IMAGE>
申请公布号 EP0045691(A2) 申请公布日期 1982.02.10
申请号 EP19810401233 申请日期 1981.07.30
申请人 THOMSON-CSF 发明人 LACHENAL, JEAN-LOUIS
分类号 H03F1/52;H03F3/50;(IPC1-7):H03F3/50 主分类号 H03F1/52
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