| 摘要 |
PURPOSE:To convert serial data having optional number of bits into parallel data at high speed by outputting the parallel data at the time of counting burst clock pulses by the number according to the number of bits of the serial data. CONSTITUTION:The serial data RXD is given to a burst clock pulse generation part 2 and an S/P conversion part 6. The generation part 2 generates the burst clock pulse BCK and gives it to the conversion part 6. The conversion part 6 sequentially shifts the data RXD according to the pulse BCK. At this time, a frame bit counter part 4 counts the pulse BCK and when the counted value reaches a set value of a counting number set part 5, the counter part 4 gives an FRC signal to a control logic part 3, which generates the signals S0, S1 and DST. The generation part 2 stops generating the pulse BCK with the signal DST and the conversion part 6 latches the converted data with the signal S0 so as to output the latched parallel data according to the signal DST. |
