发明名称 Post-silicon methods for adjusting the rise/fall times of clock edges
摘要 A method for eliminating races commences with the testing of an integrated circuit for races. If a clock signal which is produced by the integrated circuit is deemed to be a cause of races, at least one transistor region is clipped from an output driver of a clock gater which produces the clock signal. The clipping is performed by reconstructing at least one mask which is used to define the output driver during fabrication of the integrated circuit. In a similar fashion, a method for increasing the rise/fall time of clock edges in an integrated circuit commences with the identification of a clock signal with a clock edge having a poor rise/fall time. The rise/fall time of such a clock edge is increased by clipping at least one transistor region from an output driver of a clock gater which produces the clock signal. Once again, the clipping is performed by reconstructing at least one mask which is used to define the output driver during fabrication of the integrated circuit.
申请公布号 US6331800(B1) 申请公布日期 2001.12.18
申请号 US20000620932 申请日期 2000.07.21
申请人 HEWLETT-PACKARD COMPANY 发明人 RADJASSAMY RAJAKRISHNAN
分类号 H01L21/66;(IPC1-7):H01L25/00 主分类号 H01L21/66
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