发明名称 PARALLEL ANALOG/DIGITAL CONVERTER
摘要 PROBLEM TO BE SOLVED: To provide an analog/digital converter(ADC), which has a sparkle suppression ability equivalent to that of a full bit gray code conversion system and prevents entangling of wiring and increase in pipeline delay. SOLUTION: A register string 2 for generating a reference voltage Vref to be compared with an analog input signal Vin is folded (n) times or multiple times corresponding to a number (n) of high-order bits of an output bit ADB of the relevant ADC. This device has a first encoder 3-8 for encoding high-order (n) bits and outputting a gray code, second encoders 3-1 to 3-7 for encoding and outputting low-order bits, a first output circuit 4 for converting the gray code outputted from the first encoder to a binary code and generating high-order (n) bits ADB[5]-ADB[3], and a second output circuit 5 for generating low-order bits ADB[2]-ADB[0] while using the digital signal ADB[3] generated from the first output circuit and the output of the second encoders.
申请公布号 JP2002016497(A) 申请公布日期 2002.01.18
申请号 JP20000168691 申请日期 2000.06.06
申请人 SONY CORP 发明人 GENDAI YUUJI
分类号 H03M1/36;H03M1/14 主分类号 H03M1/36
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