| 摘要 |
There is provided a logic circuit causing the same delay time as a conventional logic circuit and acting as a D flip-flop circuit with a data-selecting function. A logic circuit having the circuitry shown in FIG. 6 will be described briefly. Two transmission gates TG 10 a (TG 10 b) and TG 11 and two inverters IV 10 and IV 11 are used to define a data propagation path from an input port I 1 (I 2 ) to an output port O 1 . Thus, four logic gates are located along the path in the same manner as they are in a conventional D flip-flop circuit. The transmission gate TG 10 a (TG 10 b) is controlled using a NOR circuit 12 a that inputs a clock CLK and a select signal /sel that is the reverse of a select signal sel (NOR circuit 12 b that inputs the clock CLK and the select signal sel). The transmission gate TG 11 is controlled with the clock CLK. Either of two input data items is selected based on the select signals, and then output. When a D flip-flop circuit with a data-selecting function that causes the same delay time as a conventional D flip-flop circuit is adapted to a pipeline circuit, the action of the pipeline circuit can be speeded up.
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