| 摘要 |
The present invention relates to system clocking in computer systems. In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first should fail. More redundancy even to the Dynamic Clock Switching Circuit (DCSC) ( 14 ) and the wiring ( 17 ) from there to multiple, PLL-( 12 ) free clock chips ( 22 ) is provided. Instead of only one DCSC ( 14 ) and one single wiring ( 17 ), two of them ( 14 - 0, 14 - 1; 17 - 0, 17 - 1 ) are used combined with a further particular logic present on each clock chip ( 22 ), which in combination generate two synchronous, fine-tuned, minimum-shifted clock signals and select always the first of them to arrive at a FlipFlop controlling the output for clock distribution wiring.
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