| 发明名称 | Apparatus to reduce retention failure in complementary resistive memory | ||
| 摘要 | Described is an apparatus which comprises: a complementary resistive memory bit-cell; and a sense amplifier coupled to the complementary resistive memory bit-cell, wherein the sense amplifier includes: a first output node; and a first transistor which is operable to cause a deterministic output on the first output node. | ||
| 申请公布号 | US9373395(B1) | 申请公布日期 | 2016.06.21 |
| 申请号 | US201514638942 | 申请日期 | 2015.03.04 |
| 申请人 | Intel Corporation | 发明人 | Augustine Charles;Wu Wei;Tomishima Shigeki;Liu Shih-Lien L.;Tschanz James W. |
| 分类号 | G11C13/00;G11C11/419 | 主分类号 | G11C13/00 |
| 代理机构 | Green, Howard & Mughal, LLP | 代理人 | Green, Howard & Mughal, LLP |
| 主权项 | 1. An apparatus comprising: a complementary resistive memory bit-cell; and a sense amplifier coupled to the complementary resistive memory bit-cell, wherein the sense amplifier includes: a first output node; anda first transistor which is operable to cause a deterministic output on the first output node. | ||
| 地址 | Santa Clara CA US | ||