| 摘要 |
The circuit includes a buffer with double output/input speed for facilitating the data input to the transformation device. N registers are connected in series, the first register is coupled with output end of a first selector by one input end, operating by adopting serial input one bit and parallel output N bits; one second selector with one first input end, one second input end and one output end. The first input end accepts the first bit of N bits output from the first register, and either the first or the second input end for input; N second registers, each of which has one input end, one first output end and one second output end, that is coupled with output end of the second selector by one input end, and coupled with output end of each first register without supplying the second selector input by the rest input ends in order to get one N bit input. Each first input end of the front N/2 registers is coupled to generate one first bus, each second input end coupled to generate one second bus, each first input end of the back N/2 registers is coupled to generate one third bus, each second input end coupled to generate one fourth bus to make the bus with N/2 bit capacity.
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