发明名称 CONTROL CIRCUIT FOR MULTIPLEXED ARITHMETIC AND LOGIC UNIT
摘要 PURPOSE:To continue the execution of a microprocessor by using the outputs of a normal multiplex device and to prevent a titled circuit from the regeneration of errors by comparing outputs of the multiplexing device to demarcate faults. CONSTITUTION:Data from registers 1, 2 are inputted to arithmetic and logic units (ALU) 31, 32 and outputs from respective units are inputted to a comparator 4 and an output switching circuit 5, respectively. A collated result is outputted from the comparator 4 and, if the result is normal, a control circuit 6 is actuated and the output switching circuit 5 adop an output from one previously fixed unit, the ALU31 or ALU32, and sends the output to a data bus D-BUS. When a fault is detected by the comparator 4, a diagnosing means is executed by an output signal from a starting circuit 7 and either of the normal units, ALU31 or ALU32, is discriminated. The control circuit 6 actuates the output switching circuit 5 by said discriminated signal and sends an output result form the normal ALU31 or ALU32 to the D-BUS.
申请公布号 JPS5827249(A) 申请公布日期 1983.02.17
申请号 JP19810124584 申请日期 1981.08.08
申请人 FUJITSU KK 发明人 TANIYAMA YUKIO;WADA TADAHIRO
分类号 G06F11/20;G06F11/16 主分类号 G06F11/20
代理机构 代理人
主权项
地址