发明名称 PHASE CONTROL SYSTEM OF DECCA TRANSMITTER
摘要 PURPOSE:To allow the phase of an actual or preparatory signal of a Decca transmitter to automatically match with a reference signal, by judging the tolerant phase error range of the output of a reference oscillator and the output of an actual or preparatory oscillator and correcting the phase error of both oscillator on the basis of the judge result. CONSTITUTION:The phase error of the 0.2f signal outputted from an actual 0.2f oscillator 21 or a preparatory 0.2f oscillator 31 through a change-over circuit 4 and the reference 0.2f signal from a reference 0.2f generator 1 is detected by a phase detection circuit 7 and, when said phase error is out of a tolerant range, a judge circuit 8 generates high level judge output. A notch register 11 and a reset matrix 10 are operated corresponding to said output, and the estimation notch code from the register 11 and the count number of the 6f signal from a counter circuit 9 through a multiplier 12 are added and, when the added value reaches 30, the matrix 10 generates a timing signal to reset the counter circuit 9. Then, a 2f signal is generated in reset timing to automatically match the phase of an actual or preparatory signal of a Decca transmitter and a reference signal.
申请公布号 JPS60259977(A) 申请公布日期 1985.12.23
申请号 JP19840117178 申请日期 1984.06.06
申请人 FUJITSU KK 发明人 NIITSUMA SUSUMU;OOHASHI WATARU
分类号 G01S5/10;G01S1/30 主分类号 G01S5/10
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