| 摘要 |
PURPOSE:To decrease the bit rate of a transmission line and also to simplify an interpolation digital filter by saving high-order m-bits at each N-th sample data of a prescribed rate and sending the result while remaining low-order n bits. CONSTITUTION:For example, high-order 4 bits are thrown away at each 3 samples from 8-bit sample data S1-S12, the low-order 4 bits are left and a data stream saved to the data quantity of 7/8 is read in a digital filter DF. In this case, when the data S4 is in the center tap CC of a shift register 30, 4 sample data S2, S3, S5, S6 before and after the data S4 are outputted from an adder circuit 45 as an interpolation value of the data S4. Then the interpolated value and the low-order 4 bits are synthesized by a synthesis circuit 46 to interpolate the original high-order bit and the result is outputted from an output terminal OUT via a switch 47a as complete data.
|
