| 摘要 |
PURPOSE:To improve the processing speed of a CPU by saving troubles for generating address data and an R/W signal from the subsequent data transfer when addresses where data is transferred between the CPU and memory are continuous. CONSTITUTION:At a clock T1 the CPU 1 transmits the address data to the memory 2 through an address bus ADD. At a clock T2 the CPU 1 sets a memory read signal inversion MEMR at a level L and indicates the memory 2 to act reading. At the end of a clock T3 the CPU fetches the read data from the memory 2. At the beginning of a clock T4 a memory succession signal inversion MEMS is set at a level H, and the CPU 1 reports that the 1st data fetching is completed to the memory 2. In the half way of the clock T4 the CPU 1 sets the inversion MEMS at the level L again, indicates the next address with respect to the memory 2, and fetches the 2nd data at the and of the clock T4. Then at the beginning of a clock T5 the inversion MEMR and the inversion MEMS are set at the level H, and the read action of the memory 2 is completed.
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