| 摘要 |
PURPOSE:To remarkably curtail the number of wirings by providing a first switch for outputting parallel data to a bit selective line at the time of read, and a second switch for connecting an output of a decoder to the bit selective line at the time of write. CONSTITUTION:At the time of write of series data, when a WRITE terminals is set to '1' and X0-X2 terminals and Y0-Y1 terminals are varied as C-E, F and G respectively, data of an SX terminal is supplied to an inverter 381 through an inverter 384. At the time, t1, the X0 terminal is shifted from '1' to '0', and thereafter, written in a data store bit 370. Thereafter, in the same way, the data is written one after another in each store bit of a third frame to the time t2, and written in a second frame at t2 to t3, and in a first frame 100 at t3 to t4. On the other hand, at the time of read-out, the WRITE terminal is set to '0', and frame selective data is supplied to Y0 and Y1. In such a way, at the time of read-out of parallel data and write of series data, by executing them by using a common line, the number of wiring can be curtailed remarkably. |
