| 摘要 |
PURPOSE:To execute magnification/reduction processing according to the magnification of an arbitrary rational number by fetching a picture element, which is sent out from a first memory by a first clock, into the second memory by the second clock. CONSTITUTION:In order to execute magnification/reduction processing in the process of transfer from a memory 100 to a memory 110, the clocks of various frequencies are generated from a fundamental clock signal by a digital circuit on read and write sides. Namely, in the case of the magnification processing, the second clock is set to the peak operating frequency of the second memory 110 and the first clock is set to a frequency reduced less than the second clock respectively. In the case of the reduction processing, the first clock is set to the peak operating frequency of the first memory 100 and the second clock is set to a frequency reduced less than the first clock respectively. Thus, the magnification is precisely designated over a wide range and the magnification and reduction can be executed. Further, a circuit can be formed by the normal digital circuit. |
