| 摘要 |
PURPOSE:To shorten the delay time of transmission by bypassing the data given to a 2nd input terminal from a 1st semiconductor device via a selector means and then giving the data to a 2nd semiconductor device from the 2nd input terminal. CONSTITUTION:A selector circuit 12 selects the input data P1 given from a parallel input terminal 6 or the output data of an inverter circuit 82a and applies it to a parallel output terminal 7. At the same time, the output of the circuit 12 is applied to an exclusive NOR gate 91 via an inverter circuit 13. The output of the circuit 13 is applied to the input terminal of an inverter circuit 81a. In a normal mode the circuit 12 selects and switches the data P1 given from the terminal 6. Thus the data P1 read out of a RAM and given to the terminal 6 is given to a logic circuit from the terminal 7 via the circuit 12 only. In this case, the delay time of the circuit 12 is short and therefore the performance of a semiconductor IC device is never deteriorated even with a delay of transmission of data. |
