| 摘要 |
<p>PURPOSE:To prevent the potential of a data output point excessively lowered by providing a first switching means to charge parasitic capacitor attached on the data output point by energizing a part between the data output point of a memory cell and a power source for constant time after an address is changed. CONSTITUTION:An output signal (level of connecting point G) from an address change detection circuit 23 is always set at a high level, and it is a signal set at a low level only for prescribed time when the address is changed, and the output (level of connecting point H) of an inverter 24 is a complementary signal for the signal, and an nMOS 21 is turned off and an nMOS 22 is turned on when a first Y-selector and a second Y-selector are switched simultaneously. The charge of the parastic capacitor of a digit line is performed by the nMOS 22, and the level of a connecting point F is kept constant, and the potential of a connecting point B can be kept at a constant value when the switching of the first Y-selector and the second Y-selector are completed and the nMOS 21 is turned on. In such a way, no inversion of the output signal from an output terminal Out occurs.</p> |
