| 摘要 |
<p>PURPOSE: To improve the reliability of video signal processing by using hardware so as to detect odd/even number fields of the video signal. CONSTITUTION: A counter section 100 detects a vertical pulse signal and sets a Q output of a JK FF 30 to 'H'. A counter section 200 starts counting when a Q output of an FF 30 reaches 'H' and provides an output of a window signal whose level is maintained at 'H' at a time of 60μsec. Then a Q output of a JK FF 80 goes to 'H' only when the window signal is at 'H' and a horizontal synchronizing pulse signal is delivered as an output of an AND gate 90. Thus, an output of the AND gate 90 of a detection section 300 applies a clock signal to a DFF 95 after about 15μec when a Q output of the FF 80 goes to 'H' in the case of an even number field and after about 46μsec when a Q output of the FF 80 goes to 'H' in the case of an odd number field. Thus, an interlace scanning video signal is processed by the hardware and then odd/ even number fields are detected with high reliability.</p> |
