POWER-UP RESETTING SIGNAL GENERATING CIRCUIT OF SEMICONDUCTOR DEVICE

摘要

PROBLEM TO BE SOLVED: To obtain a power up preset signal generation circuit capable of generating an accurate power up reset signal, even in a semiconductor device using a reverse bias voltage. SOLUTION: A PMOS transistor(TR) 5 to be turned on by reverse bias voltage Vbb is connected to an output node n12 for outputting a reset signal. An NMOS TR 4b has a long-channel length. When the channel length of the TR 4b is extended, an accurate reset signal is not generated, even when voltage Vdd is boosted up to a sufficiently high level. A reset state may be held, but when a voltage Vbb starts to be generated after a sufficiently high level of the voltage Vdd, the TR 5 is turned on and pull-down operation is executed, so that no trouble is generated.