FIELD EMITTER DEVICE, AND VEIL PROCESS FOR THE FABRICATION THEREOF

摘要

A field emitter device formed by a veil process wherein a protective layer (64/66) comprising a release layer (64) is deposited on the gate electrode layer (62) for the device, with the protective layer overlying the circumscribing peripheral edge of the opening of the gate electrode layer, to protect the edge of the gate electrode layer during etching of the field emitter cavity (72) in the dielectric material layer (30) on a substrate, and during the formation of a field emitter element (40) in the cavity by depositing a field emitter material through the opening. The protective layer is readily removed subsequent to completion of the cavity etching and emitter formation steps, to yield the field emitter device. Also disclosed are various planarizing structures and methods, and current limiter compositions permitting high efficiency emission of electrons from the field emitter elements at low turn-on voltages.