发明名称 |
INTEGRATED CIRCUIT PACKAGE HAVING AN INDUCTANCE LOOP FORMED FROM A MULTI-LOOP CONFIGURATION |
摘要 |
An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from first and second wires which connect a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a third and fourth wires which connect a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a third conductor between the pins. The third conductor may include one or more bonding wires and the I/O pins are preferably ones which are adjacent one another. However, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. In another embodiment, connection between the first and second I/O pins is established by making the I/O pins have a unitary construction. In another embodiment, connection between the first and second I/O pins is established by a metallization layer located either on the surface of the package substrate or within this substrate. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controlled by the length of the inductor loop of the package. |
申请公布号 |
WO2005022597(A3) |
申请公布日期 |
2005.08.04 |
申请号 |
WO2004US27797 |
申请日期 |
2004.08.27 |
申请人 |
GCT SEMICONDUCTOR, INC.;KOO, YIDO;HUH, HYUNGKI;LEE, KANG, YOON;LEE, JEONG-WOO;PARK, JOONBAE;LEE, KYEONGHO |
发明人 |
KOO, YIDO;HUH, HYUNGKI;LEE, KANG, YOON;LEE, JEONG-WOO;PARK, JOONBAE;LEE, KYEONGHO |
分类号 |
H01L;H01L23/64;H01L29/00 |
主分类号 |
H01L |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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