发明名称 Resistor ladder interpolation for PGA and DAC
摘要 A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.
申请公布号 US7271755(B2) 申请公布日期 2007.09.18
申请号 US20040926407 申请日期 2004.08.26
申请人 发明人
分类号 H03M1/12;G06F17/17;H03K17/041;H03M1/06;H03M1/14;H03M1/20;H03M1/36;H03M1/78 主分类号 H03M1/12
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