| 发明名称 |
Apparatus and Method to Dynamically Expand Associativity of A Cache Memory |
| 摘要 |
In an embodiment, a processor includes at least one core, a cache memory, and a cache controller. Responsive to a request to store an address of a data entry into the cache memory, the cache controller is to determine whether an initial cache set of the cache memory and corresponding to the address has available capacity to store the address. Responsive to unavailability of capacity in the initial cache set, the cache controller is to generate a first alternate address associated with the data entry and to determine whether a first cache set corresponding to the first alternate address has available capacity to store the alternate address and if so to store the first alternate address in the first cache set. Other embodiments are described and claimed. |
| 申请公布号 |
US2016179666(A1) |
申请公布日期 |
2016.06.23 |
| 申请号 |
US201414573811 |
申请日期 |
2014.12.17 |
| 申请人 |
Intel Corporation |
发明人 |
Greenspan Daniel;Lossin Yoav;Fanning Blaise;Aboulenein Nagi;Torrant Marc |
| 分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A processor comprising:
at least one core; a cache memory; and a cache controller, wherein responsive to a request to store an address of a data entry into the cache memory, the cache controller is to determine whether an initial cache set corresponding to the address has available capacity to store the address in the cache memory, and responsive to unavailability of capacity in the initial cache set, the cache controller is to generate a first alternate address associated with the data entry and to determine whether a first cache set corresponding to the first alternate address has available capacity to store the alternate address and if so to store the first alternate address in the first cache set. |
| 地址 |
Santa Clara CA US |
