RECONFIGURABLE LOGIC ARCHITECTURE

摘要

The present application relates to a computing technology, and more specifically, to a reconfigurable processing unit. An apparatus according to an embodiment of technical idea of the present application includes a plurality of stacked integrated circuit dies, wherein the plurality of the stacked integrated circuit dies include a memory cell die configured to store data in a random access scheme, and a lookup table die including a random access memory array including a reconfigurable lookup table configured to perform a logical operation. The reconfigurable lookup table includes a plurality of random access memory cells configured to store a lookup table for performing the logical operation, and a local row decoder for activating at least one row of memory cells based upon a set of input signals. The lookup table stored in the plurality of the memory cells are altered into the random access memory array via a memory write operation. A reconfigurable logic architecture according to an embodiment of the present application improves a computing speed and rapidly performs data communication.