TIMING SIGNAL GENERATING CIRCUIT

摘要

PROBLEM TO BE SOLVED: To generate a required timing signal in a short set-up time by generating the timing signal having a minus delay time spuriously as against a reference clock signal. SOLUTION: When a hold signal is inputted to a sample-and-hold circuit 4 by the rising of an external clock, the signals ϕ4'...ϕ11' are outputted from the circuit 4. The signals ϕ4'...ϕ11' indicate the state of zero or one. A boundary detecting circuit 5 detects the boundary of an intermediate tap which outputs the signal indicating the 'zero state' at the point of time when sampling is executed with the boundary (operation boundary) of the intermediate tap which outputs the signal indicating the 'one state'. The intermediate tap ϕ8 is specified as a reference point corresponding to the operation state. The position of the intermediate tap ϕ8 corresponds to the position of a pulse edge n-1. The signal from the intermediate tap which is positioned prescribed stages before the tap ϕ8 is picked-up with an output selecting circuit 6. Thus, the clock signal which proceeds for the portion of a proper phase is picked-up from the midst of a delay line.