ELECTRICALLY REPROGRAMMABLE, REDUCED POWER, PROGRAMMABLE LOGIC DEVICE CIRCUIT

摘要

Large multi-input CMOS logic gates may be formed by a sequence of alternating CMOS NAND and NOR logic gates. The sequence of alternating gates may be compactly laid out in an integrated circuit to form arrays of functional AND or OR gates useful in PLAS. These arrays of CMOS gates consume low power and have response times suitable for integrated circuits. These arrays may be programmed by EEPROM or EPROM transistors or in the alternative, binary latches may be used to store information determinative of the desired programming.