| 摘要 |
PURPOSE:To change the duty ratio of clock signal pulses arbitrarily by optionally setting the ratio of the size of gate width to the size of gate length of each of a PMOS transistor and an NMOS transistor and constituting a CMOS inverter circuit. CONSTITUTION:In a CMOS inverter circuit constituted of a circuit in which three PMOS transistors 1 in Fig. a are connected and a circuit in which three NMOS transistors 6 are connected, the ratio of the gate width to the gate length of the circuit constituted of the PMOS transistors is represented by 3W/L when the ratio of the gate width to the gate length of the transistor in Fig. a is represented by W/L. The ratio of the gate width of the gate length of the circuit constituted of the NMOS transistors is represented similarly by W/3L. Accordingly, the ratio of channel conductance is represented by 3:1, and the channel conductance of the PMOS transistor is trebled to the NMOS transistor, thus accelerating rise time by treble as long as fall time. |
