发明名称 DIGITAL SIGNAL PROCESSOR
摘要 PROBLEM TO BE SOLVED: To prevent the occurrence of clip noise by making the compress/limit characteristic and the clip characteristic coincide with each other. SOLUTION: A compress/limit processing circuit 54 attenuates the level of a digital signal, and a clip processing circuit 56 clips the signal processed by the compress/limit processing circuit. A CPU sets parameters (Ki, Pi, Vt) and (λt Qi, Vth') to the compress/limit processing circuit and the clip processing circuit so that output levels of curves in the compress/limit characteristic and the clip characteristic cross in a maximum input level.
申请公布号 JPH09130184(A) 申请公布日期 1997.05.16
申请号 JP19960202945 申请日期 1996.07.12
申请人 VICTOR CO OF JAPAN LTD 发明人 TANAKA YOSHIAKI
分类号 H03G3/20;H03G3/30;H03G9/00;H03G11/00;H03H17/00 主分类号 H03G3/20
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