| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor storage device, in which only a data transfer speed is increased, without changing the clock speed of DDR-DRAMs and an internal operating speed. SOLUTION: The device has first and second DDR-DRAMs 33 and 43 in a single package 2 to output data with prescribed phases, with respect to the leading edge and the trailing edge of clocks and data input output lines are commonly connected to the DDR-DRAMs. The device is also provided with clock-generating circuits 32 and 42, which generate first clocks CLKA having a same phase and second clocks CLKB having a 1/4 phase deviation from an external clock CLK. The first DDR-DRAM outputs data during a period equivalent to a 1/4 phase from the edge of the CLKA and keeps its data output circuits in a high impedance condition during other periods. The second DDR- DRAM outputs data during an interval equivalent to a 1/4 phase from the edge of the CLKB and maintains its data output circuits to a high impedance condition in intervals other than this.</p> |
