| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a method and a device for generating a data signal which can be used in a timing verification tool and is obtained by simulating a clock signal. SOLUTION: It is desirable that the clock signal is used as data input to a function block in multiple digital circuits. Multiple timing verification tools suffer from the verification of the timing of a related circuit. The clock signal is converted into the data signal obtained by simulating the clock signal. Namely, 1) the clock signal is frequency-divided into two and a frequency-dividing clock signal is formed. 2) A frequency-dividing clock signal obtained by delaying 1/2 of the period of the clock signal and a frequency-dividing clock signal obtained by delaying complete one period of the clock signal are exclusively OR-operated. 3) The result of an exclusive OR operation is inverted. 4) The inversion of the exclusive OR operation and the clock signal are aligned and the data signal obtained by simulating the clock signal is formed.</p> |
