| 摘要 |
PROBLEM TO BE SOLVED: To provide a fixed-length delay generating circuit, capable of suppressing fluctuations in delay values caused by production conditions and environmental changes. SOLUTION: On the basis of the phase comparison of a delay clock signal D4, outputted from a variable delay circuit group 3 and a frequency divided clock signal (1/n)CLK, feedback control is applied to delay in the variable delay circuit group. At this time, since the variable delay circuit group 3 is composed of second variable delay circuits 2-1 to 2-4 for generating delays equal to a first variable delay circuit 1, the first variable delay circuit 1 adds a delay matched with a delay by means of the second variable delay circuits 2-1 to 2-4 to an input signal and outputs it simultaneously with the feedback control. Therefore, since delay control in the first variable delay circuit is performed on the basis of phase comparison, error hardly occurs in the delay values, while being hardly affected by the input signal, element parameters and environmental changes. |
