| 摘要 |
a data serial/parallel conversion means converting serial PCM data(PCMDR) into parallel PCM data(SRAMD0-7); a memory means storing the PCM data(SRAM0-7) supplied from the data serial/parallel conversion means; a signal processing means which generates a 1 address signal(DSPA0-15) and a control signal(DSPCS), and detects the signal state of a line signal having a frequency for each channel by reading the data stored in the memory means; an output means storing and latching a detect signal indicating the state of the line signal from the signal processing means; and a memory and signal processing control means which controls the memory means and the signal processing means, and generates the signals(interrupt, reset, clock) which the signal processing means demands.
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